1. Field of the Invention
The present invention relates to an equalizer and more particularly to the equalizer capable of making a filter factor for the equalizer rapidly converge and a method for setting an initial value for the equalizer.
The present application claims priority of Japanese Patent Application No. 2003-411701 filed on Dec. 10, 2003, which is hereby incorporated by reference.
2. Description of the Related Art
A transmission speed of a mobile communication device such as a portable phone is increasing every year. In particular, in the case of portable telephone communications employing a W-CDMA (Wideband Code Division Multiple Access) method, by bringing an HSDPA (High Speed Downlink Packet Access) way into the portable telephone communications, a maximum transmission speed of 14.4 Mbps has been gained. In such the case where the transmission speed is increasing, it is of importance that a signal whose quality has been degraded due to an influence by fading during the signal transmission is successfully regenerated at a side of a signal receiver. To solve these problems, in addition to a RAKE receiving method that can be realized in a comparatively easy way, an equalizer and/or interference canceler are being introduced. That is, a data receiving device is proposed in, for example, Japanese Patent Application Laid-open No. Hei06-120774, in which its equalizer is provided that can perform an excellent effect of improving an error rate, in digital communications, which is realized by setting a tap factor in a manner to match a state of a communication line and by changing a transmission characteristic to compensate for a wave distortion.
FIG. 5 is a block diagram for schematically showing configurations of a conventional NLMS (Nonlinear Least Mean Square) equalizer 50. The equalizer 50 includes a filter factor computing device 51, an equalizing filter 52, and a differential detecting circuit 53. A received signal “X(n)” is input to the filter factor computing device 51 and the equalizing filter 52. An output “W(n)” from the filter factor computing device 51 is input to the equalizing filter 52. The equalizing filter 52 outputs an output signal “y(n)”, inputs the signal “y(n)” to the differential detecting circuit 53, then detects a differential “e(n)” between the signal “y(n)” and a pilot signal diffusing code “d(n)” and inputs the differential “e(n)” to the filter factor computing device 51.
More specifically, the received signal “X(n)” to be input to the equalizer 50 is input to the equalizing filter 52. The equalizing filter 52 outputs a signal resulting from addition of all values obtained by multiplying an equalizing filter factor sequence W(n)=(W0, W1, . . . , WF-1) (F: number of filters) by the received signal “X(n)” as an output value. The equalizing filter factor sequence “W(n)” is set by the filter factor computing device 51. When an output value of the equalizing filter 52 is “y(n)”, y(n)=W(n)X(n).
Next, FIG. 6 is a block diagram for showing specified configurations of the equalizing filter 52 of FIG. 5. The equalizing filter 52 is made up of a plurality (“F−1” pieces) of delay circuits 21 being cascaded, a plurality (“F” pieces) of multipliers 22 to multiply input and output values of signals to be input to or output from these delay circuits 21 by each of corresponding filter factors W0 to WF−1, and an adder 23 to sum up values of the output signals from the plurality of multipliers 22 (not shown).
Each of the delay circuits 21 multiplies a received signal by an amount of delay corresponding to one chip time, and the received signal delayed by k(0≦k≦F−1) chips is multiplied by a filter factor WF−1−k. All results from the multiplication are summed up by the adder 23 and are output as output signals. The received signal is delayed, by one chip, up to the (F−1)-th chip.
An appropriate value, for example, a value “0” is set for all initial values W(n) of equalizing filter sequences. A signal “y(n)” output from the equalizing filter 52 is input to the differential detecting circuit 53. In the differential detecting circuit 53, a differential signal “e(n)” between an output “y(n)” from the equalizing filter 52 and a pilot signal diffusing code “d(n)” is calculated and the calculated differential signal “e(n)” is output to the filter factor computing device 51. The differential signal “e(n)” is shown by the following equation (1):e(n)=d(n)−y(n)=d(n)−W(n)X(n)  Equation 1
In the filter factor computing device 51, a filter factor is renewed according to the following Equation 2 based on a received signal sequence “X(n)” and differential signal “e(n)”, and a filter factor sequence W(n) being produced prior to the renewal:W(n+1)=W(n)+μe(n)X(n)  Equation 2where “μ” denotes a step-size parameter, which is shown by the following Equation (3):μ=α/(X(n)HX(n)+β  Equation 3where “β” denotes a stabilizing parameter (it takes on a sufficiently small positive value), α denotes a step-size parameter, and “X(n)H” denotes a transposed conjugate vector of X(n).
After the renewal, equalization by a filter and renewal of a filter factor are repeated. Moreover, for a principle of the renewal of filter factors, refer to, for example, “Base and Application of Signal Processing” (ISBN4-8173-0106-6, Pages 202 to 217) by Nisshin Shuppan Co., and a like.
In the above conventional technology, a filter factor is made to converge by setting an appropriate value for an initial value of the filter factor and by repeating operations of renewing a filter factor based on a differential between a signal (equalized signal) produced by application of equalizing filter and an ideal signal. Therefore, it takes much time before a filter factor converges to an optimum filter factor after equalization is started. As a result, a problem is presented that a quality of an equalized signal is degraded during the above time required before the convergence. To solve this problem, training time is required to make a filter factor converge prior to equalization of received data.